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| M312L2828BT0 184pin 1U Registered DDR SDRAM MODULE 1GB DDR SDRAM MODULE (128Mx72 ((64Mx72)*2)based on 64Mx4 DDR SDRAM) Registered 184pin DIMM 72-bit ECC/Parity Revision 0.0 October. 2001 - -1 - Rev. 0.0 Oct. 2001 M312L2828BT0 Revision History Revision 0.0 (Oct. 2001) 1.First release for internal usage. 184pin 1U Registered DDR SDRAM MODULE -0- Rev. 0.0 Oct. 2001 M312L2828BT0 184pin 1U Registered DDR SDRAM MODULE M312L2828BT0 DDR SDRAM 184pin DIMM 128Mx72 DDR SDRAM 184pin DIMM based on Stacked 64Mx4, 4bank, 8K refresh with SPD GENERAL DESCRIPTION The Samsung M312L2828BT0 is 128M bit x 72 Double Data Rate SDRAM high density memory modules based on first generation of 256Mb DDR SDRAM respectively. The Samsung M312L2828BT0 consists of thirty-six CMOS 64M x 4 bit with 4banks Double Data Rate SDRAMs in 66pin TSOP-II(400mil) packages, mounted on a 184pin glass-epoxy substrate. Four 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each DDR SDRAM. The M312L2828BT0 is Dual In-line Memory Modules and intend-ed for mounting into 184pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. FEATURE * Performance range Part No. Max Freq. Interface SSTL_2 M312L2828BT0-C(L)A2 133MHz(7.5ns@CL=2) M312L2828BT0-C(L)B0 133MHz(7.5ns@CL=2.5) M312L2828BT0-C(L)A0 100MHz(10ns@CL=2) * Power supply : Vdd: 2.5V 0.2V, Vddq: 2.5V 0.2V * Double-data-rate architecture; two data transfers per clock cycle * Bidirectional data strobe(DQS) * Differential clock inputs(CK and CK) * DLL aligns DQ and DQS transition with CK transition * Programmable Read latency 2, 2.5 (clock) * Programmable Burst length (2, 4, 8) * Programmable Burst type (sequential & interleave) * Edge aligned data output, center aligned data input * Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh) * Serial presence detect with EEPROM * PCB : Height 1700 (mil), double sided component PIN CONFIGURATIONS (Front side/back side) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 PIN DESCRIPTION Pin 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Front VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC /RESET VSS DQ8 DQ9 DQS1 VDDQ *CK1 */CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 Pin 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 Front Pin A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 CB0 CB1 VDD DQS8 A0 CB2 VSS CB3 BA1 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Front VDDQ /WE DQ41 /CAS VSS DQS5 DQ42 DQ43 VDD */CS2 DQ48 DQ49 VSS */CK2 *CK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL Pin 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 Back VSS DQ4 DQ5 VDDQ DQS9 DQ6 DQ7 VSS NC NC *A13 VDDQ DQ12 DQ13 DQS10 VDD DQ14 DQ15 CKE1 VDDQ *BA2 DQ20 A12 VSS DQ21 A11 DQS11 VDD DQ22 A8 DQ23 Pin 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 Back VSS A6 DQ28 DQ29 VDDQ DQS12 A3 DQ30 VSS DQ31 CB4 CB5 VDDQ CK0 /CK0 VSS DQS17 A10 CB6 VDDQ CB7 Back /RAS DQ45 VDDQ /CS0 /CS1 DQS14 VSS DQ46 DQ47 */CS3 VDDQ DQ52 DQ53 NC VDD DQS15 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DQS16 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD Pin Name A0 ~ A12 BA0 ~ BA1 DQ0 ~ DQ63 CB0 ~ CB7 DQS0 ~ DQS17 CK0,CK0 CKE0,CKE1 CS0, C S 1 RAS CAS WE VDD VDDQ VSS VREF VDDSPD SDA SCL SA0 ~ 2 VDDID RESET NC Function Address input (Multiplexed) Bank Select Address Data input/output Check bit(Data-in/data-out) Data Strobe input/output Clock input Clock enable input Chip select input Row address strobe Column address strobe Write enable Power supply (2.5V) Power Supply for DQS(2.5V) Ground Power supply for reference Serial EEPROM Power Supply (2.3V to 3.6V ) Serial data I/O Serial clock Address in EEPROM VDD identification flag Reset enable No connection KEY DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 KEY VSS DQ36 DQ37 VDD DQS13 DQ38 DQ39 VSS DQ44 * These pins are not used in this module. SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. -1- Rev. 0.0 Oct. 2001 M312L2828BT0 Functional Block Diagram VSS RS1 RS0 DQS0 DQ0 DQ1 DQ2 DQ3 DQS I/O 3 I/O 2 I/O 1 I/O 0 S DM 184pin 1U Registered DDR SDRAM MODULE DM0/DQS9 DQS I/O 3 I/O 2 I/O 1 I/O 0 S DM DQ4 DQ5 DQ6 DQ7 DQS I/O 0 I/O 1 I/O 2 I/O 3 S DM DQS I/O 0 I/O 1 I/O 2 I/O 3 S DM D0 D16 D8 D24 DQS1 DQ8 DQ9 DQ10 DQ11 DQS I/O 3 I/O 2 I/O 1 I/O 0 S DM DQS I/O 3 I/O 2 I/O 1 I/O 0 S DM DM1/DQS10 DQ12 DQ13 DQ14 DQ15 DQS I/O 0 I/O 1 I/O 2 I/O 3 S DM DQS I/O 0 I/O 1 I/O 2 I/O 3 S DM D1 D17 D9 D25 DQS2 DQ16 DQ17 DQ18 DQ19 DQS I/O 3 I/O 2 I/O 1 I/O 0 S DM DQS I/O 3 I/O 2 I/O 1 I/O 0 S DM DM2/DQS11 DQ20 DQ21 DQ22 DQ23 DQS I/O 0 I/O 1 I/O 2 I/O 3 S DM DQS I/O 0 I/O 1 I/O 2 I/O 3 S DM D2 D18 D10 D26 DQS3 DQ24 DQ25 DQ26 DQ27 DQS I/O 3 I/O 2 I/O 1 I/O 0 S DM DM3/DQS12 DQS I/O 3 I/O 2 I/O 1 I/O 0 S DM DQ28 DQ29 DQ30 DQ31 DQS I/O 0 I/O 1 I/O 2 I/O 3 S DM DQS I/O 0 I/O 1 I/O 2 I/O 3 S DM D3 D19 D11 D27 DQS4 DQ32 DQ33 DQ34 DQ35 DQS I/O 3 I/O 2 I/O 1 I/O 0 S DM DM4/DQS13 DQS I/O 3 I/O 2 I/O 1 I/O 0 S DM DQ36 DQ37 DQ38 DQ39 DQS I/O 0 I/O 1 I/O 2 I/O 3 S DM DQS I/O 0 I/O 1 I/O 2 I/O 3 S DM D4 D20 D12 D28 DQS5 DQ40 DQ41 DQ42 DQ43 DQS I/O 3 I/O 2 I/O 1 I/O 0 S DM DQS I/O 3 I/O 2 I/O 1 I/O 0 S DM DM5/DQS14 DQ44 DQ45 DQ46 DQ47 DQS I/O 0 I/O 1 I/O 2 I/O 3 S DM DQS I/O 0 I/O 1 I/O 2 I/O 3 S DM D5 D21 D13 D29 DQS6 DQ48 DQ49 DQ50 DQ51 DQS I/O 3 I/O 2 I/O 1 I/O 0 S DM DQS I/O 3 I/O 2 I/O 1 I/O 0 S DM DM6/DQS15 DQ52 DQ53 DQ54 DQ55 DQS I/O 0 I/O 1 I/O 2 I/O 3 S DM DQS I/O 0 I/O 1 I/O 2 I/O 3 S DM D6 D22 D14 D30 DQS7 DQ56 DQ57 DQ58 DQ59 DQS I/O 3 I/O 2 I/O 1 I/O 0 S DM DM7/DQS16 D7 DQS I/O 3 I/O 2 I/O 1 I/O 0 S DM DQ60 DQ61 DQ62 DQ63 D23 DQS I/O 0 I/O 1 I/O 2 I/O 3 S DM D15 DQS I/O 0 I/O 1 I/O 2 I/O 3 S DM D31 Serial PD SCL WP A0 SA0 A1 SA1 A2 SA2 SDA V DDSPD V D D /V DDQ SPD D0 - D35 D0 - D35 VREF V SS V DDID D0 - D35 D0 - D35 Strap: see Note 4 C K 0 ,C K 0 CS0 CS1 BA0-BAN A0-A12 RAS CAS CKE0 CKE1 WE PCK PCK PLL R E G I S T E R RCS0 RCS1 RBA0 - RBAn RA0 - RA12 RRAS RCAS RCKE0 RCKE1 RWE BA0-BAn: SDRAMs D0 - D35 A0-An: SDRAMs D0 - D35 R A S: SDRAMs D0 - D35 C A S: SDRAMs D0 - D35 CKE: SDRAMs D0 - D17 CKE: SDRAMs D18 - D35 WE : SDRAMs D0 - D35 RESET Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/ CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. 4. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD VDDQ. -2- Rev. 0.0 Oct. 2001 M312L2828BT0 ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Voltage on VDDQ supply relative to Vss Storage temperature Power dissipation Short circuit current 184pin 1U Registered DDR SDRAM MODULE Symbol V IN, VOUT VDD VDDQ TSTG PD IOS Value -0.5 ~ 3.6 -1.0 ~ 3.6 -0.5 ~ 3.6 -55 ~ +150 36 50 Unit V V V C W mA Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out) Recommended operating conditions(Voltage referenced to V SS=0V, T A=0 to 70C) Parameter Supply voltage(for device with a nominal V DD of 2.5V) I/O Supply voltage I/O Reference voltage I/O Termination voltage(system) Input logic high voltage Input logic low voltage Input Voltage Level, CK and CK inputs Input Differential Voltage, CK and CK inputs Input crossing point voltage, CK and CK inputs Input leakage current Output leakage current Output High Current(Normal strengh driver) ;V OUT = VT T + 0.84V Output High Current(Normal strengh driver) ;V OUT = VT T - 0.84V Output High Current(Half strengh driver) ;V OUT = V T T + 0.45V Output High Current(Half strengh driver) ;V OUT = VT T - 0.45V Symbol VDD VDDQ V REF V TT V I H(DC) VIL(DC) V I N(DC) V I D(DC) VIX(DC) II IOZ IOH IOL IOH Min 2.3 2.3 VDDQ/2-50mV V REF-0.04 VREF+0.15 -0.3 -0.3 0.3 1.15 -2 -5 -16.8 16.8 -9 Max 2.7 2.7 VDDQ/2+50mV VREF+0.04 VDDQ +0.3 V REF-0.15 VDDQ +0.3 VDDQ +0.6 1.35 2 5 Unit Note V V V V V V V V uA uA mA mA mA 3 5 1 2 4 4 IOL 9 mA Notes 1. Includes 25mV margin for DC offset on VREF, and a combined total of 50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF, both of which may result in V REF noise. VREF should be de-coupled with an inductance of 3nH. 2.V TT is not applied directly to the device. V T T is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ. 5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same. 6. These charactericteristics obey the SSTL-2 class II standards. -3- Rev. 0.0 Oct. 2001 M312L2828BT0 184pin 1U Registered DDR SDRAM MODULE DDR SDRAM SPEC Items and Test Conditions Recommended operating conditions Unless Otherwise Noted, TA=0 to 70C) Conditions Operating current - One bank Active-Precharge; tRC=tRCmin;tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ,DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating current - One bank operation ; One bank open, BL=4, Reads - Refer to the following page for detailed test condition Percharge power-down standby current; All banks idle; power - down mode; CKE = IDD1 IDD2P - - IDD2F - - IDD2Q - - IDD3P - - IDD3N - - IDD4R - - IDD4W - - IDD5 IDD6 IDD7A - - -4- Rev. 0.0 Oct. 2001 M312L2828BT0 DDR SDRAM IDD spec table Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A * Module A2(DDR266@CL=2) typical 3000 3270 1560 1920 1830 1830 2100 4170 4980 4440 408 354 7140 worst 3180 3540 1650 2010 1920 1920 2280 4710 5520 5070 408 354 8040 184pin 1U Registered DDR SDRAM MODULE B0(DDR266@CL=2.5) typical 3000 3270 1560 1920 1830 1830 2100 4170 4980 4440 408 354 7140 worst 3180 3540 1650 2010 1920 1920 2280 4710 5520 5070 408 354 8040 A0(DDR200@CL=2) typical 2730 2820 1470 1740 1650 1650 1920 3540 4080 3810 408 354 6060 worst 2910 3000 1560 1830 1740 1740 2010 3990 4530 4170 408 354 6780 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Notes Optional IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. < Detailed test conditions for DDR SDRAM IDD1 & IDD7A > IDD1 : Operating current: One bank operation 1. Typical Case : Vdd = 2.5V, T=25' C 2. Worst Case : Vdd = 2.7V, T= 10' C 3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. lout = 0mA 4. Timing patterns - DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing *50% of data changing at every burst - DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing *50% of data changing at every burst - DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing *50% of data changing at every burst Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP -5- Rev. 0.0 Oct. 2001 M312L2828BT0 184pin 1U Registered DDR SDRAM MODULE IDD7A : Operating current: Four bank operation 1. Typical Case : Vdd = 2.5V, T=25' C 2. Worst Case : Vdd = 2.7V, T= 10' C 3. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not changing. lout = 0mA 4. Timing patterns - DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRRD = 2*tCK, tRCD= 3*tCK, Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing *100% of data changing at every burst - DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing *100% of data changing at every burst - DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing *100% of data changing at every burst Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP AC Operating Conditions Parameter/Condition Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals. Input Differential Voltage, CK and CK inputs Input Crossing Point Voltage, CK and CK inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 0.7 0.5*VDDQ-0.2 Min VREF + 0.31 VREF - 0.31 VDDQ+0.6 0.5*VDDQ+0.2 Max Unit V V V V Note 3 3 1 2 Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same. 3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz. -6- Rev. 0.0 Oct. 2001 M312L2828BT0 184pin 1U Registered DDR SDRAM MODULE (VDD=2.5V, VDDQ=2.5V, T A= 0 to 70 C) Value 0.5 * V DDQ 1.5 VREF+0.31/V REF -0.31 VREF Vtt See Load Circuit Unit V V V V V Note AC OPERATING TEST CONDITIONS Parameter Input reference voltage for Clock Input signal maximum peak swing Input Levels(VIH/VIL) Input timing measurement reference level Output timing measurement reference level Output load condition Vtt=0.5*VDDQ RT=50 Output Z0=50 CLOAD=30pF VREF =0.5*VDDQ Output Load Circuit (SSTL_2) 11. Input/Output CAPACITANCE Parameter (VDD=2.5, VDDQ=2.5V, T A= 25C, f=1MHz) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 COUT1 COUT2 Min 6 5 5 8 12 12 12 Max 8 7 7 10 14 14 14 Unit pF pF pF pF pF pF pF Input capacitance(A0 ~ A 12 , BA0 ~ BA1,RAS,CAS, WE ) Input capacitance(CKE0 , CKE1) Input capacitance( CS0, CS1) Input capacitance( CLK0, /CLK0) Input capacitance(DM 0 ~DM 8 ) Data & DQS input/output capacitance(DQ0~DQ63) Data input/output capacitance(CB 0 ~CB7) -7- Rev. 0.0 Oct. 2001 M312L2828BT0 184pin 1U Registered DDR SDRAM MODULE (These AC charicteristics were tested on the Component) -TCA0 (DDR200) Min 70 80 120K 48 20 20 15 2 1 1 12 12 0.55 0.55 +0.75 +0.75 +0.5 1.1 0.6 1.25 0.45 0.45 -0.8 -0.8 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 1.1 0.9 1.1 1.1 tACmax - 400ps tACmax - 400ps tACmin - 400ps tACmin - 400ps 0.5 0.5 4.5 5 1.5 1.0 0.7 0.67 4.5 5 1.5 tACmax - 400ps tACmax - 400ps 1.1 10 12 12 0.55 0.55 +0.8 +0.8 +0.6 1.1 0.6 1.25 120K Max Min 65 75 45 20 20 15 2 1 1 7.5 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 tACmin 400ps tACmin 400ps 0.5 0.5 1.0 0.7 0.67 4.5 5 1.5 tACmax - 400ps tACmax - 400ps 1.1 12 12 0.55 0.55 +0.75 +0.75 +0.5 1.1 0.6 1.25 120K Max Min 65 75 45 20 20 15 2 1 1 10 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 tACmin - 400ps tACmin - 400ps 0.5 0.5 1.0 0.7 0.67 Max Unit ns ns ns ns ns ns tCK tCK tCK ns ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK tCK tCK ns ns ps ps V/ns V/ns V/ns V/ns 6 7 10 10 6 6 2 5 5 5 Note AC Timming Parameters & Specifications Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Col. address to Col. address delay Clock cycle time Clock high level width Clock low level width DQS-out access time from CK/CK Output data access time from CK/CK Data strobe edge to ouput data edge Read Preamble Read Postamble CK to valid DQS-in DQS-in setup time DQS-in hold time DQS falling edge to CK rising-setup time DQS falling edge from CK rising-hold time DQS-in high level width DQS-in low level width DQS-in cycle time Address and Control Input setup time Address and Control Input hold time Data-out high impedence time from CK/CK Data-out low impedence time from CK/CK Input Slew Rate(for input only pins) Input Slew Rate(for I/O pins) Output Slew Rate(x4,x8) Output Slew Rate(x16) Output Slew Rate Matching Ratio(rise to fall) CL=2.0 CL=2.5 Symbol tRC tRFC tRAS tRCD tRP tRRD tWR tCDLR tCCD tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPREH tDSS tDSH tDQSH tDQSL tDSC tIS tIH tHZ tLZ tSL(I) tSL(IO) tSL(O) tSL(O) tSLMR -TCA2(DDR266A) -TCB0(DDR266B) -8- Rev. 0.0 Oct. 2001 M312L2828BT0 184pin 1U Registered DDR SDRAM MODULE -TCA2(DDR266A) Min 15 0.5 0.5 1.75 10 95 75 200 15.6 7.8 tQH tHP tQHS tWPST 0.25 tHPmin -tQHS tCLmin or tCHmin 0.75 0.25 75 200 15.6 7.8 tHPmin -tQHS tCLmin or tCHmin 0.75 0.25 Max -TCB0(DDR266B) Min 15 0.5 0.5 1.75 10 Max -TCA0 (DDR200) Min 16 0.6 0.6 2 10 116 80 200 15.6 7.8 tHPmin -tQHS tCLmin or tCHmin 0.8 Max Parameter Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS DQ & DM input pulse width Power down exit time Exit self refresh to write command Exit self refresh to bank active command Exit self refresh to read command Refresh interval time 64Mb, 128Mb 256Mb Symbol tMRD tDS tDH tDIPW tPDEX tXSW tXSA tXSR tREF Unit ns ns ns ns ns ns ns Cycle us us ns ns ns tCK Note 7,8,9 7,8,9 4 1 1 5 Output DQS valid window Clock half period Data hold skew factor DQS write postamble time 3 Note : 1. Maximum burst refresh of 8 2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. 3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. 4. A write command can be applied with tRCD satisfied after this command. 5. For registered DINNs, tCL and tCH are 45% of the period including both the half period jitter (t JIT(HP) ) of the PLL and the half period jitter due to crosstalk (t JIT(crosstalk)) on the DIMM. -9- Rev. 0.0 Oct. 2001 M312L2828BT0 6. Input Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate (V/ns) 0.5 0.4 0.3 tIS (ps) 0 +50 184pin 1U Registered DDR SDRAM MODULE tIH (ps) 0 +50 +100 +100 This derating table is used to increase t IS /tIH in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 7. I/O Setup/Hold Slew Rate Derating I/O Setup/Hold Slew Rate (V/ns) 0.5 0.4 0.3 tDS (ps) 0 +75 +150 tDH (ps) 0 +75 +150 This derating table is used to increase t DS /tDH in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 8. I/O Setup/Hold Plateau Derating I/O Input Level (mV) 280 tDS (ps) +50 tDH (ps) +50 This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF 310mV for a duration of up to 2ns. 9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating Delta Rise/Fall Rate (ns/V) 0 0.25 0.5 tDS (ps) 0 +50 +100 tDH (ps) 0 +50 +100 This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate. 10. This parameter is fir system simulation purpose. It is guranteed by design. - 10 Rev. 0.0 Oct. 2001 M312L2828BT0 Command Truth Table COMMAND Register Register Extended MRS Mode Register Set Auto Refresh Entry Refresh Self Refresh Exit 184pin 1U Registered DDR SDRAM MODULE (V=Valid, X=Don t Care, H=Logic High, L=Logic Low) CKEn-1 CKEn CS RAS CAS WE BA0,1 A10/AP A11, A12 A9 ~ A0 Note H H H X X H L H X X L L L L H L L L H X L H L L L H X H L L L H H X H H V V OP CODE OP CODE X 1, 2 1, 2 3 3 3 3 L H H X Row Address L Column Address A0 ~A9 ,A1 1 Column Address A0 ~A9 ,A1 1 Bank Active & Row Addr. Read & Column Address Write & Column Address Burst Stop Bank Selection Precharge All Banks Entry Active Power Down Exit Entry Precharge Power Down Mode Exit DM No operation (NOP) : Not defined Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable L L 4 4 4 4, 6 7 H L H H H H X X X L L L H L H H L X V X X H X V X L H H X V X X H X V L L V X V L H X L X V X X H X 5 H L H L H L X X H L H L X L H H H X L H X V X X H X H X 8 9 9 X H Note : 1. OP Code : Operand Code. A 0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "High" and BA 1 is "Low" at read, write, row active and precharge, bank B is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A 10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM. - 11 Rev. 0.0 Oct. 2001 M312L2828BT0 PACKAGE DIMENSIONS 184pin 1U Registered DDR SDRAM MODULE Units : Inches (Millimeters) 5.25 0.006 (133.350 0.15) 5.171 (131.350) 5.077 (128.950) 0.118 (3.00) (2.50 Mi n) 0 .1 00 Min A B 2.500 A B 0.10 M C B A 0.268 Max (6.81 Max) ( 0.157 ) (10 .0 0) 0.39 3 0.78 (19.80) PLL (4.00 ) (17 .8 0) 0.7 (30 .4 8) 0.050 0.0039 (1.270 0.10) 0.0787 R (2.00) Reg. 1.2 ( 2.50 ) 0.26 (6.62) 0.10 0 0.250 (6.350 ) 0.157 (4.00 ) 0.039 0.002 (1.000 0.050) 0.0787 R (2.00) 0.0078 0.006 (0.20 0.15) 0.118 (3.00) 0.1496 (3.80) 2.175 0.071 (1.80 ) 0.050 (1.270) 0.1575 (4.00) 0.10 M C AM B Detail A Detail B Tolerances : 0.005(.13) unless otherwise specified The used device is 64Mx4 SDRAM, 66TSOPII SDRAM Part NO : K4H560438B-TC - 12 Rev. 0.0 Oct. 2001 M312L2828BT0 184pin 1U Registered DDR SDRAM MODULE 0ns (nominal) 184 Pin DDR Registered DIMM Clock Topolgy SDRAM stack PLL OUT1 R=120 CK0 120 CK0 R=240 120 L6 OUT `N' feedback Reg1 SDRAM stack L7 Reg2 1.5pF R=240 Note : Lenghts in inches Note * Z0=60 tD=2.2ns/ft Probe point Clock Reference Net 1.0 0.266 128 Notes* : 1. The Clock delay from the input of the PLL clock to the input of any SDRAM or register will be set to 0ns(nominal). 2. Input,output, and feedback clock lines are terminated from line to leine as shown, and not from line to ground. 3. Only one PLL output is shown per output type. Any addtional PLL outputs will be wired in a similar maner. 4. termination resistors for the PLL feedback path clocks are loacted after the pins of the PLL. - 13 Rev. 0.0 Oct. 2001 |
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